Non-volatile memory is a type of data storage device in which stored data is retained in the absence of power. That is, data that was previously written to the non-volatile memory remains stored in the memory without substantial degradation of the value of the stored data after electrical power is removed from the non-volatile memory. However, some forms of non-volatile memory may be susceptible to degradation of the value of stored data due to several factors including passage of time, disturbs caused by successive read operations to a non-volatile memory cell, disturbs caused by half-select voltages applied to non-volatile memory cells, just to name a few. For example, disturbances in a non-volatile two-terminal cross-point memory array can degrade the margins, such as read margins, associated with non-volatile two-terminal memory cells positioned in the array, thereby leading to corrupted data or incorrect data being read from the array. Margins often describe the tolerance for a memory cell to provide accurate data (e.g., data representing values for a logic “0” or a logic “1”) during, for example, a read operation when the memory cells are exposed to memory disturb effects caused by the application of a read voltage across the two terminals of the memory cell. Generally, data retention is the ability of the memory to retain stored data without corruption of the stored data due to any number of effects including but not limited to the aforementioned passage of time or disturbs to the memory cells caused by applied voltages.
To maintain appropriate read margins in environments that degrade memory cells, some conventional approaches test whether a specific memory cell can deliver voltages and/or currents that satisfy margin requirements during a margin test operation. Usually, the margin test operation is performed as a separate process that consumes memory support circuitry resources during the margin testing, typically at the expense of other memory device processes. Further, conventional approaches typically require dedicated sense amplifiers and reference cells to determine the read margins. Thus, the drawbacks to conventional approaches usually include an increased amount of circuitry and/or delayed memory operations (e.g., reading and writing) due to the margin testing. As one example, for memory cells that store data as a resistance value where a logic “0” is a high resistance (e.g., 10 MΩ) and a logic “1” is a low resistance (e.g., 100 kΩ), for a constant value of a read voltage (e.g., 3 V), a low read current will flow through a memory cell storing the high resistance logic “0” and a high read current will flow thorough a memory cell storing the low resistance logic “1”. Accordingly, circuitry, such as a sense amp, can determine the value of stored data in a memory cell by sensing the magnitude of read current flowing through the memory cell during a read operation. However, if the resistance values for logic “0” and logic “1” drift in value and/or are corrupted by disturbs, then the magnitude of the read currents will also be affected and the sense amp may not be able to accurately determine the value of the stored data. Consequently, incorrect data values may be obtained during read operations to the memory due to corrupted data.
There are continuing efforts to improve data retention in non-volatile memory.
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